Digital Design
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ISBN：9787040114171
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简介
进入21世纪，尤其随着我国加入WTO，信息产业的国际竞争将更加激烈。我国信息产业虽然在20世纪末取得了迅猛发展，但与发达国家相比，甚至与印度、爱尔兰等国家相比，还有很大差距。国家信息化的发展速度和信息产业的国际竞争能力，最终都将取决于信息科学技术人才的质量和数量。引进国外信息科学和技术优秀教材，在有条件的学校推动开展英语授课或双语教学，是教育部为加快培养大批高质量的信息技术人才采取的一项重要举措。
为此，教育部要求由高等教育出版社首先开展信息科学和技术教材的引进试点工作。同时提出了两点要求，一是要高水平，二是要低价格。在高等教育出版社和信息科学技术引进教材专家组的努力下，经过比较短的时间，第一批引进的20多种教材已经陆续出版。这套教材出版后受到了广泛的好评，其中有不少是世界信息科
学技术领域著名专家、教授的经典之作和反映信息科学技术最新进展的优秀作品，代表了目前世界信息科学技术教育的一流水平，而且价格也是最优惠的，与国内同类自编教材相当。
这项教材引进工作是在教育部高等教育司和高教社的共同组织下，由国内信息科学技术领域的专家、教授广泛参与，在对大量国外教材进行多次遴选的基础上，参考了国内和国外著名大学相关专业的课程设置进行系统引进的。其中，John Wiley公司出版的贝尔实验室信息科学研究中心副总裁Silberchatz教授的经典著作《操作系统概念》，是我们经过反复谈判，做了很多努力才得以引进的。William Stallings先生曾编写了在美国深受欢迎的信息科学技术系列教材，其中有多种教材获得过美国教材和学术著作者协会颁发的计算机科学与工程教材奖，这批引进教材中就有他的两本著作。留美中国学者Jiawei Han先生的《数据挖掘》是该领域中具有里程碑意义的著作。由达特茅斯学院刀Thomas Cormen和麻省理工学院、哥伦比亚大学的几 位学者共同编著的经典著作《算法导论》，在经历了11年的锤炼之后于2001年出版了第二版。目前任教于美国Massachusetts大学的James Kurose教授，曾在美国三所高校先后10次获得杰出教师或杰出教学奖，由他主编的《计算机网络》出版后，以其体系新颖、内容先进而倍受欢迎。在努力降低引进教材售价方面，高等教育出版社做了大量和细致的工作。这套引进的教材体现了权威性、系统性、先进性和经济性等特点。
教育部也希望国内和国外的出版商积极参与此项工作，共同促进中国信息技术教育和信息产业的发展。我们在与外商的谈判工作中，不仅要坚定不移地引进国外最优秀的教材，而且还要千方百计地将版权转让费降下来，要让引进教材的价格与国内自编教材相当，让广大教师和学生负担得起。中国的教育市场巨大，外国出版
公司和国内出版社要通过扩大发行数量取得效益。
在引进教材的同时，我们还应做好消化吸收，注意学习国外先进的教学思想和教学方法，提高自编教材的水平，使我们的教学和教材在内容体系上，在理论与实践的结合上，在培养学生的动手能力上能有较大的突破和创新。
目录
preface
1 binary systems
1-1 digital systems
1-2 binary numbers
1-3 number base conversions
1-4 octal and hexadecimal numbers
1-5 complements
1-6 signed binary numbers
1-7 binary codes
1-8 binary storage and registers
1-9 binary logic
2 boolean alcebra and locic cates
2-1 basic definitions
2-2 axiomatic definition of boolean algebra
2-3 basic theorems and properties
of boolean algebra
2-4 boolean functions
2-5 canonical and standard forms
2-6 other logic operations
2-7 digital logic cates
.2-8 integrated circuits
3 cate-level minimization
3-1 the map method
3-2 four-variable map
3-3 five-variable map
3-4 product of sums simplification
3-5 don't-care conditions
3-6 nand and nor implementation
3-7 other two-level implementations
3-8 exclusive-or function
3-9 hardware description language (hdl)
4 combinational locic
4-1 combinational circuits
4-2 analysis procedure
4-3 design procedure
4-4 binary adder-subtractor
4-5 decimal adder
4-6 binary multiplier
4-7 magnitude comparator
4-8 decoders
4-9 encoders
4-10 multiplexers
4-11 hdl for combinational circuits
5 synchronous sequential locic
5-1 sequential circuits
5-2 latches
5-3 flip-flops
5-4 analysis of clocked sequential circuits
5-5 hdl for sequential circuits
5-6 state reduction and assignment
5-7 design procedure
6 recisters and counters
6-1 registers
6-2 shift registers
6-3 ripple counters
6-4 synchronous counters
6-5 other counters
6-6 hdl for registers and counters
7 memory and procrammable logic
7-1 introduction
7-2 random-access memory
7-3 memory decoding
7-4 error detection and correction
7-5 read-only memory
7-6 programmable logic array
7-7 programmable array logic
7-8 sequential programmable devices
8 recister transfer level
8-1 register transfer level (rtl) notation
8-2 register transfer level in hdl
8-3 algorithmic state machines (asm)
8-4 design example
8-5 hdl description of design example
8-6 binary multiplier
8-7 control logic
8-8 hdl description of binary multiplier
8-9 design with muitiplexers
9 asynchronous sequentlal locic
9-1 introduction
9-2 anaiysis procedure
9-3 circuits with latches
9-4 design procedure
9-5 reduction of state and flow tables
9-6 race-free state assignment
9-7 hazards
9-8 design exampie
10 dicital intecrated circuits
10-1 introduction
10-2 special characteristics
10-3 bipolar-transistor characteristics
10-4 rtl and dtl circuits
10-5 transistor-transistor logic (ttl)
10-6 emitter-coupled logic (ecl)
10-7 metal-oxide semiconductor (mos)
10-8 complementary mos (cmos)
10-9 cmos transmission cate circuits
10-10 switch-lever modeling with hdl
11 laboratory experiments
11-0 introduction to experiments
11-1 binary and decimal numbers
11-2 digital logic gates
11-3 simplification of boolean functions
11-4 combinational circuits
11-5 code conveners
11-6 design with multiplexers
11-7 adders and subtractors
11-8 flip-flops
11-9 sequential circuits
11-10 counters
11-11 shift registers
11-12 serial addition
11-13 memory unit
11-14 lamp handball
11-15 clock-pulse cenerator
11-16 parallel adder and accumulator
11-17 binary multiplier
11-18 asynchronous sequential circuits
11-19 verilog hdl simulation experiments
12 standard craphic symbols
12-1 rectangular-shape symbols
12-2 qualifying symbols
12-3 dependency notation
12-4 symbols for combinational elements
12-5 symbols for flip-flops
12-6 symbols for registers
12-7 symbols for counters
12-8 symbol for ram
answers to selected problems
index
1 binary systems
1-1 digital systems
1-2 binary numbers
1-3 number base conversions
1-4 octal and hexadecimal numbers
1-5 complements
1-6 signed binary numbers
1-7 binary codes
1-8 binary storage and registers
1-9 binary logic
2 boolean alcebra and locic cates
2-1 basic definitions
2-2 axiomatic definition of boolean algebra
2-3 basic theorems and properties
of boolean algebra
2-4 boolean functions
2-5 canonical and standard forms
2-6 other logic operations
2-7 digital logic cates
.2-8 integrated circuits
3 cate-level minimization
3-1 the map method
3-2 four-variable map
3-3 five-variable map
3-4 product of sums simplification
3-5 don't-care conditions
3-6 nand and nor implementation
3-7 other two-level implementations
3-8 exclusive-or function
3-9 hardware description language (hdl)
4 combinational locic
4-1 combinational circuits
4-2 analysis procedure
4-3 design procedure
4-4 binary adder-subtractor
4-5 decimal adder
4-6 binary multiplier
4-7 magnitude comparator
4-8 decoders
4-9 encoders
4-10 multiplexers
4-11 hdl for combinational circuits
5 synchronous sequential locic
5-1 sequential circuits
5-2 latches
5-3 flip-flops
5-4 analysis of clocked sequential circuits
5-5 hdl for sequential circuits
5-6 state reduction and assignment
5-7 design procedure
6 recisters and counters
6-1 registers
6-2 shift registers
6-3 ripple counters
6-4 synchronous counters
6-5 other counters
6-6 hdl for registers and counters
7 memory and procrammable logic
7-1 introduction
7-2 random-access memory
7-3 memory decoding
7-4 error detection and correction
7-5 read-only memory
7-6 programmable logic array
7-7 programmable array logic
7-8 sequential programmable devices
8 recister transfer level
8-1 register transfer level (rtl) notation
8-2 register transfer level in hdl
8-3 algorithmic state machines (asm)
8-4 design example
8-5 hdl description of design example
8-6 binary multiplier
8-7 control logic
8-8 hdl description of binary multiplier
8-9 design with muitiplexers
9 asynchronous sequentlal locic
9-1 introduction
9-2 anaiysis procedure
9-3 circuits with latches
9-4 design procedure
9-5 reduction of state and flow tables
9-6 race-free state assignment
9-7 hazards
9-8 design exampie
10 dicital intecrated circuits
10-1 introduction
10-2 special characteristics
10-3 bipolar-transistor characteristics
10-4 rtl and dtl circuits
10-5 transistor-transistor logic (ttl)
10-6 emitter-coupled logic (ecl)
10-7 metal-oxide semiconductor (mos)
10-8 complementary mos (cmos)
10-9 cmos transmission cate circuits
10-10 switch-lever modeling with hdl
11 laboratory experiments
11-0 introduction to experiments
11-1 binary and decimal numbers
11-2 digital logic gates
11-3 simplification of boolean functions
11-4 combinational circuits
11-5 code conveners
11-6 design with multiplexers
11-7 adders and subtractors
11-8 flip-flops
11-9 sequential circuits
11-10 counters
11-11 shift registers
11-12 serial addition
11-13 memory unit
11-14 lamp handball
11-15 clock-pulse cenerator
11-16 parallel adder and accumulator
11-17 binary multiplier
11-18 asynchronous sequential circuits
11-19 verilog hdl simulation experiments
12 standard craphic symbols
12-1 rectangular-shape symbols
12-2 qualifying symbols
12-3 dependency notation
12-4 symbols for combinational elements
12-5 symbols for flip-flops
12-6 symbols for registers
12-7 symbols for counters
12-8 symbol for ram
answers to selected problems
index
Digital Design
- 名称
- 类型
- 大小
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