Cover
The Design Warrior\\u0027s Guide to FPGAs
Contents
Preface
Acknowledgments
Chapter 1 Introduction
What are FPGAs?
Why are FPGAs of interest?
What can FPGAs be used for?
What\\u0027s in this book?
What\\u0027s not in this book?
Who\\u0027s this book for?
Chapter 2 Fundamental Concepts
The key thing about FPGAs
A simple programmable function
Fusible link technologies
Antifuse technologies
Mask-programmed devices
PROMs
EPROM-based technologies
EEPROM-based technologies
FLASH-based technologies
SRAM-based technologies
Summary
Chapter 3 The Origin of FPGAs
Related technologies
Transistors
Integrated circuits
SRAMs, DRAMs, and microprocessors
SPLDs and CPLDs
PROMs
PLAs
PALs and GALs
Additional programmable options
CPLDs
ABEL, CUPL, PALASM, JEDEC, etc.
ASICs (gate arrays, etc.)
Full custom
The Micromatrix and Micromosaic
Gate arrays
Standard cell devices
Structured ASICs
FPGAs
Platform FPGAs
FPGA-ASIC hybrids
How FPGA vendors design their chips
Chapter 4 Alternative FPGA Architectures
A word of warning
A little background information
Antifuse versus SRAM versus ...
SRAM-based devices
Security issues and solutions with SRAM-based devices
Antifuse-based devices
EPROM-based devices
E2PROM/FLASH-based devices
Hybrid FLASH-SRAM devices
Summary
Fine-, medium-, and coarse-grained architectures
MUX- versus LUT-based logic blocks
MUX-based
LUT-based
MUX-based versus LUT-based?
3-, 4-, 5-, or 6-input LUTs?
LUT versus distributed RAM versus SR
CLBs versus LABs versus slices
A Xilinx logic cell
An Altera logic element
Slicing and dicing
CLBs and LABs
Distributed RAMs and shift registers
Fast carry chains
Embedded RAMs
Embedded multipliers, adders, MACs, etc.
Embedded processor cores (hard and soft)
Hard microprocessor cores
Soft microprocessor cores
Clock trees and clock managers
Clock trees
Clock managers
General-purpose I/O
Configurable I/O standards
Configurable I/O impedances
Core versus I/O supply voltages
Gigabit transceivers
Hard IP, soft IP, and firm IP
System gates versus real gates
FPGA years
Chapter 5 Programming (Configuring) an FPGA
Weasel words
Configuration files, etc.
Configuration cells
Antifuse-based FPGAs
SRAM-based FPGAs
The quickness of the hand deceives the eye
Programming embedded (block) RAMs, distributed RAMs, etc.
Multiple programming chains
Quickly reinitializing the device
Using the configuration port
Serial load with FPGA as master
Parallel load with FPGA as master
Parallel load with FPGA as slave
Serial load with FPGA as slave
Using the JTAG port
Using an embedded processor
Chapter 6 Who Are All the Players?
Introduction
FPGA and FPAA vendors
FPNA vendors
Full-line EDA vendors
FPGA-specialist and independent EDA vendors
FPGA design consultants with special tools
Open-source, free, and low-cost design tools
Chapter 7 FPGA Versus ASIC Design Styles
Introduction
Coding styles
Pipelining and levels of logic
What is pipelining?
Pipelining in electronic systems
Levels of logic
Asynchronous design practices
Asynchronous structures
Combinational loops
Delay chains
Clock considerations
Clock domains
Clock balancing
Clock gating versus clock enabling
PLLs and clock conditioning circuitry
Reliable data transfer across multiclock domains
Register and latch considerations
Latches
Flip-flops with both "set" and "reset" inputs
Global resets and initial conditions
Resource sharing (time-division multiplexing)
Use it or lose it!
But wait, there\\u0027s more
State machine encoding
Test methodologies
Chapter 8 Schematic-Based Design Flows
In the days of yore
The early days of EDA
Front-end tools like logic simulation
Back-end tools like layout
CAE + CAD = EDA
A simple (early) schematic-driven ASIC flow
A simple (early) schematic-driven FPGA flow
Mapping
Packing
Place-and-route
Timing analysis and post-place-and-route simulation
Flat versus hierarchical schematics
Clunky flat schematics
Sleek hierarchical (block-based) schematics
Schematic-driven FPGA design flows today
Chapter 9 HDL-Based Design Flows
Schematic-based flows grind to a halt
The advent of HDL-based flows
Different levels of abstraction
A simple (early) HDL-based ASIC flow
A simple (early) HDL-based FPGA flow
Architecturally aware FPGA flows
Logic versus physically aware synthesis
Graphical design entry lives on
A positive plethora of HDLs
Verilog HDL
VHDL and VITAL
Mixed-language designs
UDL/I
Superlog and SystemVerilog
SystemC
Points to ponder
Be afraid, be very afraid
Serial versus parallel multiplexers
Beware of latch inference
Use constants wisely
Consider resource sharing
Last but not least
Chapter 10 Silicon Virtual Prototyping for FPGAs
Just what is an SVP?
ASIC-based SVP approaches
Gate-level SVPs (from fast-and-dirty synthesis)
Gate-level SVPs (from gain-based synthesis)
Cluster-level SVPs
RTL-based SVPs
FPGA-based SVPs
Interactive manipulation
Incremental place-and-route
RTL-based FPGA SVPs
Chapter 11 C/C++ etc.–Based Design Flows
Problems with traditional HDL-based flows
C versus C++ and concurrent versus sequential
SystemC-based flows
What is SystemC (and where did it come from)?
SystemC 1.0
SystemC 2.0
Levels of abstraction
SystemC-based design-flow alternatives
Love it or loath it
Augmented C/C++-based flows
What do we mean by augmented C/C++?
Augmented C/C++ design-flow alternatives
Pure C/C++-based flows
Different levels of synthesis abstraction
Mixed-language design and verification environments
Chapter 12 DSP-Based Design Flows
Introducing DSP
Alternative DSP implementations
Pick a device, any device, but don\\u0027t let me see which one
System-level evaluation and algorithmic verification
Software running on a DSP core
Dedicated DSP hardware
DSP-related embedded FPGA resources
FPGA-centric design flows for DSPs
Domain-specific languages
System-level design and simulation environments
Floating-point versus fixed-point representations
System/algorithmic level to RTL (manual translation)
System/algorithmic level to RTL (automatic-generation)
System/algorithmic level to C/C++ etc.
Block-level IP environments
Don\\u0027t forget the testbench!
Mixed DSP and VHDL/Verilog etc. environments
Chapter 13 Embedded Processor-Based Design Flows
Introduction
Hard versus soft cores
Hard cores
Soft microprocessor cores
Partitioning a design into its hardware and software components
Hardware versus software views of the world
Using an FPGA as its own development environment
Improving visibility in the design
A few coverification alternatives
RTL (VHDL or Verilog)
C/C++, SystemC, etc.
Physical chip in hardware modeler
Instruction set simulator
A rather cunning design environment
Chapter 14 Modular and Incremental Design
Handling things as one big chunk
Partitioning things into smaller chunks
Modular design
Incremental design
On the downside
There\\u0027s always another way
Chapter 15 High-Speed Design and Other PCB Considerations
Before we start
We were all so much younger then
The times they are a-changing
FPGA Xchange
Other things to think about
High-speed designs
SI analysis
SPICE versus IBIS
Startup power
Use of internal termination impedances
Pushing data around in parallel versus serial
Chapter 16 Observing Internal Nodes in an FPGA
Lack of visibility
Multiplexing as a solution
Special debugging circuitry
Virtual logic analyzers
VirtualWires
The problem
The VirtualWires solution
Chapter 17 Intellectual Property
Sources of IP
Handcrafted IP
IP at the unencrypted RTL level
IP at the encrypted RTL level
IP at the unplaced-and-unrouted netlist level
IP at the placed-and-routed netlist level
IP core generators
Miscellaneous stuff
Chapter 18 Migrating ASIC Designs to FPGAs and Vice Versa
Alternative design scenarios
FPGA only
FPGA-to-FPGA
FPGA-to-ASIC
ASIC-to-FPGA
Chapter 19 Simulation, Synthesis, Verification, etc. Design Tools
Introduction
Simulation (cycle-based, event-driven, etc.)
What are event-driven logic simulators?
A brief overview of the evolution of event-driven logic simulators
Logic values and different logic value systems
Mixed-language simulation
Alternative delay formats
Cycle-based simulators
Choosing the best logic simulator in the world!
Synthesis (logic/HDL versus physically aware)
Logic/HDL synthesis technology
Physically aware synthesis technology
Retiming, replication, and resynthesis
Choosing the best synthesis tool in the world!
Timing analysis (static versus dynamic)
Static timing analysis
Statistical static timing analysis
Dynamic timing analysis
Verification in general
Verification IP
Verification environments and creating testbenches
Analyzing simulation results
Formal verification
Different flavors of formal verification
But just what is formal verification, and why is it so cool?
Terminology and definitions
Alternative assertion/property specification techniques
Static formal versus dynamic formal
Summary of different languages, etc.
Miscellaneous
HDL to C conversion
Code coverage, etc.
Performance analysis
Chapter 20 Choosing the Right Device
So many choices
If only there were a tool
Technology
Basic resources and packaging
General-purpose I/O interfaces
Embedded multipliers, RAMs, etc.
Embedded processor cores
Gigabit I/O capabilities
IP availability
Speed grades
On a happier note
Chapter 21 Gigabit Transceivers
Introduction
Differential pairs
Multiple standards
8-bit/10-bit encoding, etc.
Delving into the transceiver blocks
Ganging multiple transceiver blocks together
Configurable stuff
Comma detection
Output differential swing
On-chip termination resistors
Pre-emphasis
Equalization
Clock recovery, jitter, and eye diagrams
Clock recovery
Jitter and eye diagrams
Chapter 22 Reconfigurable Computing
Dynamically reconfigurable logic
Dynamically reconfigurable interconnect
Reconfigurable computing
Chapter 23 Field-Programmable Node Arrays
Introduction
Algorithmic evaluation
picoChip\\u0027s picoArray technology
An ideal picoArray application: Wireless base stations
The picoArray design environment
QuickSilver\\u0027s ACM technology
You define the mix of nodes
The system controller node, input/output nodes, etc.
Spatial and temporal segmentation
Creating and running applications on an ACM
But wait, there\\u0027s more
It\\u0027s silicon, Jim, but not as we know it!
Chapter 24 Independent Design Tools
Introduction
ParaCore Architect
Generating floating-point processing functions
Generating FFT functions
A Web-based interface
The Confluence system design language
A simple example
But wait, there\\u0027s more
Free evaluation copy
Do you have a tool?
Chapter 25 Creating an Open-Source-Based Design Flow
How to start an FPGA design shop for next to nothing
The development platform: Linux
Obtaining Linux
The verification environment
Icarus Verilog
Dinotrace and GTKWave
Covered code coverage
Verilator
Python
Formal verification
Open-source model checking
Open-source automated reasoning
What actually is the problem?
Access to common IP components
OpenCores
OVL
Synthesis and implementation tools
FPGA development boards
Miscellaneous stuff
Chapter 26 Future FPGA Developments
Be afraid, be very afraid
Next-generation architectures and technologies
Billion-transistor devices
Super-fast I/O
Super-fast configuration
More hard IP
Analog and mixed-signal devices
ASMBL and other architectures
Different granularity
Embedding FPGA cores in ASIC fabric
Embedding FPNA cores in ASIC and FPGA fabric and vice versa
MRAM-based devices
Don\\u0027t forget the design tools
Expect the unexpected
Appendix A Signal Integrity 101
Before we start
Capacitive and inductive coupling (crosstalk)
Chip-level effects
Chip-level effects are RC (resistance-capacitance) dominated
Increased sidewall capacitive coupling
Crosstalk-induced glitches
Crosstalk-induced delay effects
Multiaggressor scenarios
And let\\u0027s not forget the Miller effect
Board-level effects
Board-level effects are LC (inductance-capacitance) dominated
A different way of thinking about things
Capacitive and inductive coupling effects
The anti-Miller effect
Transmission line effects
Things you can do to make life easier
Appendix B Deep-Submicron Delay Effects 101
Introduction
The evolution of delay specifications
A potpourri of definitions
Signal slopes
Input switching thresholds
Intrinsic versus extrinsic delays
Pn-Pn and Pt-Pt delays
State and slope dependency
Alternative interconnect models
The lumped-load model
The distributed RC model
The pure LC model
The RLC model
DSM delay effects
Path-specific Pn-Pn delays
Threshold-dependent Pn-Pn delays
Slope-dependent Pn-Pn delays
State-dependent Pn-Pn delays
Path-dependent drive capability
Slope-dependent drive capability
State-dependent drive capability
State-dependent switching thresholds
State-dependent terminal parasitics
The effect of multi-input transitions on Pn-Pn delays
The effect of multi-input transitions on drive capability
Reflected parasitics
Summary
Appendix C Linear Feedback Shift Registers 101
The Ouroboras
Many-to-one implementations
More taps than you know what to do with
One-to-many implementations
Seeding an LFSR
FIFO applications
Modifying LFSRs to sequence 2 n values
Accessing the previous value
Encryption and decryption applications
Cyclic redundancy check applications
Data compression applications
Built-in self-test applications
Pseudorandom-number-generation applications
Last but not least
Glossary
About the Author
Index
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